The present invention relates to a charge pump circuit, and more particularly, to a charge pump for converting a voltage with a capacitor.
FIG. 1A is a schematic circuit diagram of a first example of a prior art charge pump circuit 501, and FIG. 1B is a schematic circuit diagram of a second example of a prior art charge pump circuit 502. The charge pump circuit 501 includes two diodes D1, D2, a capacitor C1, and an output capacitor Cout. The charge pump circuit 502 includes p-channel MOS transistors T1, T2 in lieu of the diodes D1, D2.
A clock signal CLK is provided via the capacitor C1 to a node N1 between the diodes D1, D2 of the charge pump circuit 501 or between the transistors T1, T2 of the charge pump circuit 502. The charge pump circuits 501, 502 each convert a power supply voltage VDD, the value of which is a high logic level of the clock signal CLK, to a negative voltage “−VDD”.
FIG. 2 is a combined timing and waveform chart illustrating the operation of the charge pump circuits 501, 502.
In FIG. 2, prior to time t1, the clock signal CLK is high, and the diode D1 (transistor TR1) is activated. In this state, the voltage Vn1 at node N1 is substantially equal to zero volts (ground voltage GND), and the output voltage Vout is also substantially equal to the ground voltage GND.
When the clock signal CLK falls to a logic low level (zero volts) at time t1, the capacitor C1 decreases the node voltage Vn1 to substantially −VDD. In this state, the diode D1 (transistor TR1) is deactivated, and the diode D2 (transistor TR2) is activated. Thus, the output voltage Vout becomes equal to substantially −VDD, as shown in FIG. 2. This charges the output capacitor Cout to −VDD.
When the clock signal CLK goes high again at time t2, the capacitor C1 substantially increases the node voltage Vn1 to the ground voltage GND. This deactivates the diode D2 (transistor TR2) and holds the output voltage Vout at the vicinity of the charge voltage −VDD of the output capacitor Cout.
Then, when the clock signal CLK goes low again at time t3, the node voltage Vn1 decreases again to substantially −VDD. In this state, the diode D1 (transistor TR1) is deactivated, and the diode D2 (transistor TR2) is activated. Thus, the output capacitor Cout is charged to −VDD. The repeated charging of the output capacitor Cout holds the output voltage Vout at substantially −VDD.
Except for the externally connected capacitors C1, Cout, an integrated circuit (IC) may be configured from the charge pump circuits 501, 502. Accordingly, the charge pump circuits 501, 502 are used in an IC as a voltage conversion circuit for obtaining a desired voltage value. For example, the charge pump circuits 501, 502 are used in a charge-coupled device (CCD) driver IC or a memory IC.
The charge pump circuits 501, 502 enable step-up and step-down of a voltage with a simple circuit configuration. However, voltage decreases resulting from a threshold voltage value Vth of the diodes D1, D2 (or the transistors T1, T2) may decrease the absolute value of the output voltage Vout. In the charge pump circuits 501, 502, the absolute logic value of the output voltage Vout is VDD−2Vth and decreased from the maximum logic value VDD by 2Vth. The decrease in the absolute value of the output voltage Vout decreases the voltage conversion efficiency of the charge pump circuit.
To avoid the decrease of the output voltage (absolute value) that is caused by the threshold value Vth, for example, instead of forming a diode connection with the transistors T1, T2, the p-channel MOS transistors T1, T2 of FIG. 1B may be used in the conventional manner. In this case, the through current generated when controlling the activation and deactivation of the transistors T1, T2 decreases voltage conversion efficient and lowers transistor reliability.